The present invention is directed to integrated circuits and, more particularly, to an integrated circuit with a reset generation circuit for scan mode exit.
Integrated circuits (ICs) are commonly tested using automatic test equipment (ATE) during manufacture to detect hardware defects. A device under test (DUT) may have design-for-testability (DFT) features that facilitate the automatic testing. The DFT features often include scan test registers that are connected in one or more scan chains to test the functionality of the registers as well as to gain access to internal nodes of the IC. Test patterns are shifted into the IC through the scan chains during test mode operation. The DUT is returned to functional operation during one or more capture clock cycles, and the resulting signals are shifted out through the scan chains and checked against valid outputs.
One industry standard that is widely used in automatic testing of ICs (and other circuits) is the Joint Test Action Group (JTAG) standard IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. A device that complies with the JTAG standard has a JTAG interface with a test access port (TAP) controller and a TAP that has four pins to which the ATE is connected and that are necessarily present (test data in—TDI, test data out—TDO, test clock—TCK, and test mode select—TMS). A fifth, test reset PIN (TRST*) is optional and enables the JTAG interface registers to be cleared asynchronously, for example, after running one test pattern and before starting another. The JTAG interface is often also used in debugging software and may be used in development environments for embedded software.
It is important to reduce the number of external pins or leads on ICs, especially for some types of devices. It is desirable to be able to reset test configurations without a dedicated test reset pin (such as TRST*).
A power on reset signal (POR_B) is typically generated by an IC when power is applied to it, after a phase where the power was down, to reset the test configurations. One conventional technique of resetting test configurations without a dedicated test reset pin includes instructions in the test program between different test patterns to interrupt the power supply to the DUT to exit the test program. The power supply is then re-established by the ATE and the power on reset signal POR_B clears the test registers (as opposed to clearing the registers with the TRST* pin, when the pin is not provided). However, the time for the power down to clear the registers and for the ensuing power-up to re-establish stable operation is non-trivial. Moreover, this type of reset may need to be performed frequently during testing, which significantly prolongs the overall test time.
A conventional technique for test reset keeps the JTAG controller (or other test controller) completely out of the scan. However, in that case the JTAG interface itself cannot be tested by the scan coverage, which leaves the risk of undetected defects in the JTAG interface. Since the JTAG controller needs to be active during scan mode, the four JTAG pins TDI, TDO, TCK and TMS cannot be reused for scan chain operations.
Another conventional technique enables test mode to be entered, exited and reset by a series of over voltage excursions, and test mode exit being enabled by a chip enable signal. However, this technique cannot be used for ICs that require a high immunity to noise and interference.
IEEE standard 1581 defines a method for testing the interconnection of discrete, complex memory ICs where additional pins for testing are not available. However, IEEE 1581 does not provide a solution to the issues discussed above. Thus, it would be advantageous to have an IC in which the JTAG controller is covered by scan, yet the IC does not require a separate test reset pin.